Instruction sets may be categorized by the best cardinal of operands absolutely defined in instructions.
(In the examples that follow, a, b, and c are (direct or calculated) addresses apropos to anamnesis cells, while reg1 and so on accredit to apparatus registers.)
0-operand (zero-address machines), so alleged assemblage machines: All addition operations booty abode application the top one or two positions on the stack; 1-operand advance and pop instructions are acclimated to admission memory: advance a, advance b, add, pop c.
1-operand (one-address machines), so alleged accumulator machines, accommodate aboriginal computers and abounding baby microcontrollers: best instructions specify a distinct appropriate operand (that is, constant, a register, or a anamnesis location), with the absolute accumulator as the larboard operand (and the destination if there is one): amount a, add b, abundance c. A accompanying chic is applied assemblage machines which generally acquiesce a distinct absolute operand in addition instructions: advance a, add b, pop c.
2-operand — abounding CISC and RISC machines abatement beneath this category:
CISC — generally amount a,reg1; add reg1,b; abundance reg1,c on machines that are bound to one anamnesis operand per instruction; this may be amount and abundance at the aforementioned location
CISC — move a->c; add c+=b.
RISC — Requiring absolute anamnesis loads, the instructions would be: amount a,reg1; amount b,reg2; add reg1,reg2; abundance reg2,c
3-operand, acceptance added good reclaim of data:.4
CISC — It becomes either a distinct instruction: add a,b,c, or added typically: move a,reg1; add reg1,b,c as best machines are bound to two anamnesis operands.
RISC — addition instructions use registers only, so absolute 2-operand load/store instructions are needed: amount a,reg1; amount b,reg2; add reg1+reg2->reg3; abundance reg3,c; clashing 2-operand or 1-operand, this leaves all three ethics a, b, and c in registers accessible for added reuse4.
added operands—some CISC machines admittance a array of acclamation modes that acquiesce added than 3 operands (registers or anamnesis accesses), such as the VAX "POLY" polynomial appraisal instruction.
Due to the ample cardinal of $.25 bare to encode the three registers of a 3-operand instruction, RISC processors application 16-bit instructions are consistently 2-operand machines, such as the Atmel AVR, the TI MSP430, and some versions of the ARM Thumb. RISC processors application 32-bit instructions are usually 3-operand machines, such as processors implementing the Power Architecture, the SPARC architecture, the MIPS architecture, the ARM architecture, and the AVR32 architecture.
Each apprenticeship specifies some cardinal of operands (registers, anamnesis locations, or actual values) explicitly. Some instructions accord one or both operands implicitly, such as by actuality stored on top of the assemblage or in an absolute register. When some of the operands are accustomed implicitly, the cardinal of defined operands in an apprenticeship is abate than the arity of the operation. When a "destination operand" absolutely specifies the destination, the cardinal of operand specifiers in an apprenticeship is beyond than the arity of the operation. Some apprenticeship sets accept altered numbers of operands for altered instructions.
(In the examples that follow, a, b, and c are (direct or calculated) addresses apropos to anamnesis cells, while reg1 and so on accredit to apparatus registers.)
0-operand (zero-address machines), so alleged assemblage machines: All addition operations booty abode application the top one or two positions on the stack; 1-operand advance and pop instructions are acclimated to admission memory: advance a, advance b, add, pop c.
1-operand (one-address machines), so alleged accumulator machines, accommodate aboriginal computers and abounding baby microcontrollers: best instructions specify a distinct appropriate operand (that is, constant, a register, or a anamnesis location), with the absolute accumulator as the larboard operand (and the destination if there is one): amount a, add b, abundance c. A accompanying chic is applied assemblage machines which generally acquiesce a distinct absolute operand in addition instructions: advance a, add b, pop c.
2-operand — abounding CISC and RISC machines abatement beneath this category:
CISC — generally amount a,reg1; add reg1,b; abundance reg1,c on machines that are bound to one anamnesis operand per instruction; this may be amount and abundance at the aforementioned location
CISC — move a->c; add c+=b.
RISC — Requiring absolute anamnesis loads, the instructions would be: amount a,reg1; amount b,reg2; add reg1,reg2; abundance reg2,c
3-operand, acceptance added good reclaim of data:.4
CISC — It becomes either a distinct instruction: add a,b,c, or added typically: move a,reg1; add reg1,b,c as best machines are bound to two anamnesis operands.
RISC — addition instructions use registers only, so absolute 2-operand load/store instructions are needed: amount a,reg1; amount b,reg2; add reg1+reg2->reg3; abundance reg3,c; clashing 2-operand or 1-operand, this leaves all three ethics a, b, and c in registers accessible for added reuse4.
added operands—some CISC machines admittance a array of acclamation modes that acquiesce added than 3 operands (registers or anamnesis accesses), such as the VAX "POLY" polynomial appraisal instruction.
Due to the ample cardinal of $.25 bare to encode the three registers of a 3-operand instruction, RISC processors application 16-bit instructions are consistently 2-operand machines, such as the Atmel AVR, the TI MSP430, and some versions of the ARM Thumb. RISC processors application 32-bit instructions are usually 3-operand machines, such as processors implementing the Power Architecture, the SPARC architecture, the MIPS architecture, the ARM architecture, and the AVR32 architecture.
Each apprenticeship specifies some cardinal of operands (registers, anamnesis locations, or actual values) explicitly. Some instructions accord one or both operands implicitly, such as by actuality stored on top of the assemblage or in an absolute register. When some of the operands are accustomed implicitly, the cardinal of defined operands in an apprenticeship is abate than the arity of the operation. When a "destination operand" absolutely specifies the destination, the cardinal of operand specifiers in an apprenticeship is beyond than the arity of the operation. Some apprenticeship sets accept altered numbers of operands for altered instructions.
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